Key ResponsibilitiesDesign and implement low-power Design-for-Test (DFT) architectures to ensure efficient and scalable testability in complex SoC designs.Integrate key DFT components such as scan chains, boundary scan logic, and memory BIST (MBIST) into RTL and gate-level designs.Perform pre- and post-layout verification of scan and MBIST logic to ensure functional correctness and timing closure.Support silicon bring-up by working with test engineers to v
Key ResponsibilitiesDesign and implement low-power Design-for-Test (DFT) architectures to ensure efficient and scalable testability in complex SoC designs.Integrate key DFT components such as scan chains, boundary scan logic, and memory BIST (MBIST) into RTL and gate-level designs.Perform pre- and post-layout verification of scan and MBIST logic to ensure functional correctness and timing closure.Support silicon bring-up by working with test engineers to v
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