Key Responsibilities
- Design and implement low-power Design-for-Test (DFT) architectures to ensure efficient and scalable testability in complex SoC designs.
- Integrate key DFT components such as scan chains, boundary scan logic, and memory BIST (MBIST) into RTL and gate-level designs.
- Perform pre- and post-layout verification of scan and MBIST logic to ensure functional correctness and timing closure.
- Support silicon bring-up by working with test engineers to validate and debug test vectors on actual hardware.
Qualifications
- Bachelor’s or Master’s degree in Electrical or Computer Engineering, with at least 10 years of hands-on experience in DFT implementation for advanced SoC designs.
- Deep understanding of DFT methodologies including scan compression, boundary scan, and memory BIST (MBIST).
- Proven experience in designing low-power and hierarchical DFT architectures.
- Skilled in developing and validating scan ATPG and MBIST test environments.
If you are interested in the position , kindly send your CVs in to jasper.soh(@)randstad.com.sg Please include your availability, expected salary and reason for leaving your current jobWe regret that only shortlisted candidates will be contactedEA: 94C3609 / Reg: R25154228
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